Tuesday, 13:15 - 13:40 h, Room: H 3012


Stefan Hougardy
Transistor level layout: Algorithms and complexity


In hierarchical VLSI design a leaf cell is a functional unit at the lowest level of the hierarchy. A leaf cell implements a specific function. It is built from a small number of transistors that are connected by wires.
The problem of automatically generating transistor level layouts of leaf cells has been studied for several decades. It requires the solution of hard problems as for example Steiner tree packing problems or linear arrangement problems. We give an overview of some of the algorithmic problems appearing in the transistor level layout of leaf cells and discuss why current VLSI technology requires new algorithms.


Talk 1 of the invited session Tue.2.H 3012
"Algorithms for transistor-level layout" [...]
Cluster 2
"Combinatorial optimization" [...]


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